1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device comprising a printed circuit board type ball grid array (hereinafter referred to as a BGA) and a package for the semiconductor device and, more particularly, to a method for manufacturing a semiconductor device comprising a printed circuit board type BGA package in which a plurality of printed wiring boards are laminated, and a package for the semiconductor device.
2. Description of the Background Art
FIG. 57 is a sectional view showing the structure of a semiconductor device according to the prior art. In FIG. 57, the reference numeral 1 designates a semiconductor device comprising a printed circuit board type BGA package, the reference numeral 2 designates a chip provided in the semiconductor device 1, the reference numeral 3 designates a slug on which the chip 2 is placed, the reference numeral 4 designates a die bonding resin which bonds the chip 2 to the slug 3, the reference numeral 5 designates a frame that is provided around the chip 2 and has one of main surfaces to which the slug 3 is bonded, the reference numeral 6 designates an adhesive bonding the frame 5 to the slug 3, the reference numeral 7 designates a solder ball formed on the other main surface of the frame 5, the reference numeral 8 designates a wire electrically connecting the chip 2 to the frame 5, the reference numeral 9 designates a cavity formed in the central portion of the frame 5 to housing the chip 2 therein, the reference numeral 10 designates a sealing resin for filling in the cavity 9 to seal the chip 2, and the reference numeral 11 designates a dam which is formed on the other main surface of the frame 5 enclosing an opening and preventing the sealing resin 10 from flowing out.
The frame 5 comprises two double-sided printed circuit boards 15 and 16 which are laminated, and a prepreg 17 for bonding them. The double-sided printed circuit board 15 has wiring layers 19 and 20 provided on both sides of an insulating substrate 18. The double-sided printed circuit board 16 has wiring layers 22 and 23 provided on both sides of an insulating substrate 21.
The wiring layers 19 and 20 and the wiring layers 22 and 23 provided on both sides of the double-sided printed circuit boards 15 and 16 are wired by interstitial via holes, respectively. The double-sided printed circuit boards 15 and 16 are wired by a through hole 24.
The exchange of a signal and power between the chip 2 and a board on which the semiconductor device 1 is placed occurs through the wire 8, the wiring layers 19, 20, 22 and 23, the through hole 24, an interstitial via hole 25, the solder ball 7 and the like.
A method for manufacturing the printed circuit board type BGA package according to the prior art shown in FIG. 57 will be described below with reference to FIGS. 43 to 57.
First of all, a double-sided printed circuit board 15 having copper foils 30 and 31 laminated on both sides is prepared (see FIG. 43).
Then, a hole 32 for an interstitial via hole which penetrates the double-sided printed circuit board 15 is formed (see FIG. 44). The double-sided printed circuit board 15 on which the hole 32 is formed is plated with copper so that a copper plated layer 33 is formed. Thus, an interstitial via hole 25 is formed (see FIG. 45). As shown in FIG. 46, the interstitial via hole 25 is filled with a resin 34. Consequently, no gap which penetrates the double-sided printed circuit board 15 is present. Then, a wiring layer 20 of the double-sided printed circuit board 15 is patterned (see FIG. 47).
After performing the same steps as the steps shown in FIGS. 43 to 47, a double-sided printed circuit board 16 is prepared in which the interstitial via hole 25 that is filled with the resin 34 is formed and a wiring layer 22 is patterned (see FIG. 48). The double-sided printed circuit board 16 comprises copper foils 35 and 36, and a copper plated layer 37 formed thereon.
Then, the double-sided printed circuit board 15 shown in FIG. 47 and the double-sided printed circuit board 16 shown in FIG. 48 are bonded together by prepreg 17. Consequently, a laminated printed circuit board 38 is formed as an aggregate of the double-sided printed circuit boards 15 and 16 (see FIG. 49). A chamber 39 for forming a cavity 9 shown in FIG. 57 is provided between the double-sided printed circuit boards 15 and 16 in the central portion of the laminated printed circuit board 38. A hole 40 which penetrates the laminated printed circuit board 38 is formed in a region 41 of the laminated printed circuit board 38 where the prepreg 17 is inserted (see FIG. 50). The laminated printed circuit board 38 in which the hole 40 is formed is plated with copper so that a copper plated layer 42 is formed. Thus, a through hole 24 is formed (see FIG. 51). The laminated printed circuit board 38 is immersed in a plating solution so as to be plated with copper. However, the interstitial via hole 25 has been filled with a resin so that the chamber 39 has been sealed. For this reason, the plating solution does not invade the chamber 39.
Subsequently, the through hole 24 is filled with a resin 43 as shown in FIG. 52. Then, a wiring layer 19 is patterned (see FIG. 53). At the same time, the copper foil 30 and the copper plated layers 33 and 42 of the wiring layer 19 which are provided in an upper region 44 of the chamber 39 are removed. An insulating substrate 18 provided in the upper region 44 is opened by a router so that an opening 45 is formed. After that, nickel-gold plating is performed so that a nickel-gold plated layer 46 is formed on the copper plated layers 37 and 42 (see FIG. 54).
As shown in FIG. 55, a wiring layer 23 is patterned. At the same time, the copper foil 35 and the copper plated layers 37 and 42 which are provided in a lower region 47 of the chamber 39 are removed. As shown in FIG. 56, an opening 48 is formed in the lower region 47 so that a frame 5 is completed. A slug 3 is bonded to the frame 5 with an adhesive 6.
The chip 2 is bonded to the slug 3 with a die bonding resin 4 and the chip 2 is connected to the nickel-gold plated layer 46 by a wire 8. After a dam 11 is put in place, the cavity 9 is filled with a sealing resin 10 so that a package is sealed. Then, a solder ball 7 is formed on the nickel-gold plated layer 46 of the wiring layer 19. Thus, the printed circuit board type BGA package is completed (see FIG. 57).
The semiconductor device and the method for manufacturing the semiconductor device according to the prior art have the above-mentioned structure. Therefore, the copper plated layers 33 and 37 are formed on the copper foils 31 and 36 of the wiring layers 20 and 22, and the copper plated layer 33 or 37 and the copper plated layer 42 are formed doubly on the copper foils 30 and 37 of the wiring layers 19 and 23. Consequently, the thicknesses of the wiring layers 19, 20, 22 and 23 become greater. For this reason, it is hard to reduce the pitches of patterns formed on the wiring layers 19, 20, 22 and 23.
The above-mentioned problem will be described below with reference to FIGS. 58 and 59. FIG. 58 is a sectional view showing the state in which a wiring layer 50A is formed by a copper foil 52 and a copper plated layer 51 and a pattern is formed at a minimum pitch. The formed pattern has a predetermined inclination 53 which depends on the conditions of patterning. In FIG. 58, the reference numeral 55 designates a space between patterns which is required at the minimum, and the reference numeral 54 designates a pattern pitch. FIG. 59 is a sectional view showing the state in which a wiring layer 50B is formed by only the copper foil 52 and a pattern is formed at a minimum pitch. Similarly to the section of the pattern shown in FIG. 58, the pattern shown in FIG. 59 has a predetermined inclination 53 which depends on the conditions of patterning. In FIG. 59, the reference numeral 55 designates a space between patterns which is required at the minimum, and the reference numeral 56 designates a pattern pitch. As seen from a comparison between FIGS. 58 and 59, the pitch 54 is greater than the pitch 56. When the thickness of the wiring layer is increased, it becomes harder to reduce the pitch of the wiring pattern.
Furthermore, the through hole 24 and the interstitial via hole 5 should be plated separately at the plating step. Consequently, the number of manufacturing steps is increased.
In addition, it is necessary to immerse the laminated printed circuit board 38 in the plating solution when forming the through hole 24 at the manufacturing steps. For this reason, a step of filling the interstitial via hole 25 with the resin cannot be omitted.